Abbrev. for emitter-coupled logic. A high-speed logic family available in the form of integrated circuits based on bipolar transistors. The fast switching speeds are achieved by means of a design that avoids driving the transistors into saturation.
The basic circuit element is based on a difference amplifier, as shown in the diagram (ignoring dashed lines). In this symmetrical circuit the combined emitter current flowing through the resistor Re is substantially constant. If the voltage Vi is equal to Vref then each transistor, Q1 and Q2, conducts by the same amount and the output is at Vref. If Vi is increased above Vref by more than about 0.1 volts, Q1 will be turned on while Q2 turns off. As a result Vo increases to V+. Similarly if Vi is decreased below Vref by more than about 0.1 volts, Vo will decrease to some value largely determined by VEE, Re, and Rc.
By placing transistors in parallel with Q1, as shown by the dashed lines, an ECL OR gate is produced. Additional buffering is required on the gate output to provide the correct voltage swings for subsequent gate inputs.
ECL provided the highest speed of any silicon-based logic family but its high power dissipation and the need for high levels of integration mean that it has been superseded by CMOS technology.
ECL.Two-input ECL OR gate